DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 518

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
Rev. 3.00, 03/04, page 476 of 830
Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 to set the acknowledge data.
Clear the HNDS bit in ICXR to 0 to cancel the handshake function.
Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1.
When ICDR is read (dummy data is read), reception is started, and the receive clock is
output, and data received, in synchronization with the internal clock.
The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been
set to 1, an interrupt request is sent to the CPU.
Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt
reception.
If IRTR flag is 1, read ICDR receive data.
Clear the IRIC flag. When the flag is set as (1) in step [3], the master device outputs the 9th
clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal.
Data can be received continuously by repeating steps [3] to [6].
Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first
clock pulse for the next receive data.
Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit
value becomes valid when the rising edge of the next 9th clock pulse is input.
Read the ICDR receive data.
Clear the IRIC flag to 0.
The IRIC flag is set to 1 in either of the following cases.
(1) At the fall of the 8th receive clock pulse for one frame
(2) At the rise of the 9th receive clock pulse for one frame
(1) At the fall of the 8th receive clock pulse for one frame
(2) At the rise of the 9th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag clearing.
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next
data.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received.