DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 203

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3.2
There are following usage notes for this event counter because it uses the DTC. If these usage
notes are not permitted in some applications, use functions such as 8-bit timer event count.
1. Continuous events that are input from the same pin and out of DTC handling are ignored
2. If some events are generated in short intervals, the priority of event counter handling is not
3. If the counter overflows, this event counter counts from H'0000 without generating an
7.4
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt
request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last
consecutive transfer in the case of chain transfer), the interrupt flag that became the activation
source or the corresponding DTCER bit is cleared. The activation source flag, in the case of
RXI0, for example, is the RDRF flag in SCI_0.
When an interrupt has been designated as a DTC activation source, the existing CPU mask level
and interrupt controller priorities have no effect. If there is more than one activation source at the
same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block
diagram of DTC activation source control. For details on the interrupt controller, see section 5,
Interrupt Controller.
because the count up is operated by means of the DTC.
ordered and events are not handled in order of arrival.
interrupt.
Usage Notes
Activation Sources
Source flag cleared
IRQ interrupt
peripheral
DTVECR
On-chip
module
Figure 7.2 Block Diagram of DTC Activation Source Control
Interrupt
request
DTCER
Select
Clear
Interrupt controller
controller
Clear
DTC
Clear request
Interrupt mask
Rev. 3.00, 03/04, page 161 of 830
CPU