DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 195

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2.2
MRB selects the DTC operating mode.
Bit
7
6
5 to 0
7.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Bit Name
CHNE
DISEL
—
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
DTC Destination Address Register (DAR)
Initial
Value
Undefined
Undefined
Undefined
R/W
—
—
—
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.6.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. When this bit
is cleared to 0, a CPU interrupt request is generated
only when the specified number of data transfer ends.
Reserved
These bits have no effect on DTC operation. The write
value should always be 0.
Rev. 3.00, 03/04, page 153 of 830