DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 411

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clock synchronous mode, and smart card interface mode. The initial value of BRR is H
can be read from or written to by the CPU at all times.
Table 14.2 Relationships between N Setting in BRR and Bit Rate B
[Legend]
B:
N:
φ:
n and S:
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate settable for each frequency. Table 14.6 and 14.8 show sample N settings in
BRR in clock synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin. Tables 14.5
and 14.7 show the maximum bit rates with external clock input.
Mode
Asynchronous mode
Clock synchronous mode
Smart card interface mode
CKS1
0
0
1
1
Bit Rate Register (BRR)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
SMR Setting
CKS0
0
1
0
1
Bit Rate
B =
B =
B =
64 × 2
8 × 2
S × 2
n
0
1
2
3
φ × 10
2n – 1
2n + 1
φ × 10
φ × 10
2n – 1
× (N + 1)
× (N + 1)
6
× (N + 1)
6
6
BCP1
0
0
1
1
Error
Error (%) = {

Error (%) =
Rev. 3.00, 03/04, page 369 of 830
SMR Setting
{
B × 64 × 2
BCP0
0
1
0
1
B × S × 2
φ × 10
2n – 1
2n + 1
φ × 10
6
× (N + 1)
× (N + 1)
6
′
S
32
64
372
256
FF, and it
– 1 } × 100
–1 × 100
}