DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 183

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.5
When accessing the external address space, this LSI can extend the bus cycle by inserting one or
more wait states (T
wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin.
(1) In Normal Extended Mode
(a) Program Wait Mode: A specified number of wait states T
T
specified by the settings of the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in
WSCR2 for the 256-kbyte extended area, and the WC21 and WC20 bits in WSCR2 for the CP
extended area).
(b) Pin Wait Mode: A specified number of wait states T
and T
by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP extended area). If
the WAIT pin is low at the falling edge of φ in the last T
If the WAIT pin is held low, T
Pin wait mode is useful when inserting four or more T
states to be inserted for each external device.
2
state and T
3
AD15 to AD8
state when accessing the external address space. The number of wait states T
AD7 to AD0
Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
Wait Control
CPCS1
CS256
HWR
LWR
IOS
RD
AH
3
φ
state when accessing the external address space. The number of wait states T
W
). There are three ways of inserting wait states: Program wait insertion, pin
T
1
Address
T
Address
Address
AW
W
states are inserted until it goes high.
T
2
Read Cycle
T
3
T
4
Data
T
DSW
T
Data
Data
5
W
states, or when changing the number of T
2
T
W
or T
1
are always inserted between the T
Address
T
Address
Address
AW
W
W
state, another T
are always inserted between the
Rev. 3.00, 03/04, page 141 of 830
T
2
Write Cycle
T
3
T
4
Data
W
Data
Data
T
DSW
state is inserted.
W
T
is specified
5
W
2
is
state
W