DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 635

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.4
The D/A converter incorporates two channels of the D/A circuits and can be converted
individually.
When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are
output.
An example of D/A conversion of channel 0 is shown below. The operation timing is shown in
figure 17.2.
1. Write conversion data to DADR0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of t
3. Conversion starts immediately after DADR0 is modified. After the interval of t
4. When the DAOE bit is cleared to 0, analog output is disabled.
conversion results are output from the analog output pin DA0. The conversion results are
output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output
value is calculated by the following formula:
conversion results are output.
[Legend]
t
φ
Address
DADR0
DAOE0
DA 0
DCONV
Operation
: D/A conversion time
DADR contents/256
DADR0
write cycle
High impedance state
Figure 17.2 D/A Converter Operation Example
DACR
write cycle
Conversion data (1)
x
AVref
t
DCONV
Conversion result (1)
DADR0
write cycle
Rev. 3.00, 03/04, page 593 of 830
t
DCONV
Conversion data (2)
Conversion
result (2)
DACR
write cycle
DCONV
,
DCONV
,

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