DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 134

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.2
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
1. An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
2. An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
For instance, the state when the interrupt enable bit corresponding to each interrupt is set to 1, and
ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are
set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown
below. Figure 5.6 shows a state transition diagram.
1. All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 >
2. Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
3. Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
Figure 5.7 shows a flowchart of the interrupt acceptance operation.
Rev. 3.00, 03/04, page 92 of 830
to 0. When the I bit is set to 1, the interrupt request is held pending.
EVENTI, KIN, and WUE interrupts are enabled or disabled by the I bit.
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
IRQ1 > address break …)
0.
Exception handling execution
Interrupt Control Mode 1
All interrupt requests
or I
are accepted
Figure 5.6 State Transition in Interrupt Control Mode 1
1, UI
1
I
interrupt requests are accepted
Only NMI and address break
0
I
1, UI
I
0
0
UI
0
interrupt control level 1 interrupt
Exception handling
Only NMI, address break, and
execution or UI
requests are accepted
1