DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 620
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 16.8 Scope of LPC Interface Pin Shutdown
Notes: O: Pins shut down by the shutdown function
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by STBY or RES pin input, or WDT0 overflow)
2. LPC hardware reset (reset by LRESET pin input)
3. LPC software reset (reset by LRSTB)
4. LPC hardware shutdown
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 16.9.
Rev. 3.00, 03/04, page 578 of 830
Abbreviation
LAD3 to LAD0
LFRAME
LRESET
LCLK
SERIRQ
LSCI
LSMI
PME
GA20
CLKRUN
LPCPD
All register bits, including bits LPC3E to LPC1E, are initialized.
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
SDWNE and SDWNB bits are cleared to 0.
SDWNB bit is cleared to 0.
∆: Pins shut down only when the LPC function is selected by register setting
X: Pins not shut down
Port
PE3 to PE0 O
PE4
PE5
PE6
PE7
PD0
PD1
PD2
PD3
PD4
PD5
Scope of
Shutdown
O
X
O
O
∆
∆
∆
∆
O
X
I/O
Input
I/O
I/O
I/O
I/O
I/O
Input
Input
I/O
I/O
Input
Notes
Hi-Z
Hi-Z
LPC hardware reset function is active
Hi-Z
Hi-Z
Hi-Z, only when LSCIE = 1
Hi-Z, only when LSMIE = 1
Hi-Z, only when PMEE = 1
Hi-Z, only when FGA20E = 1
Hi-Z
Needed to clear shutdown state
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