DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 845

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 25.10 Timing of On-Chip Peripheral Modules
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 5 MHz to 33 MHz
Note:
Item
I/O ports Output data delay time
FRT
TMR
PWM,
PWMX
SCI
A/D
converter
WDT
*
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Input clock cycle Asynchronous t
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Trigger input setup time
RESO output delay time
RESO output pulse width
Only the peripheral modules that can be used in subclock operation.
Single edge
Both edges
Single edge
Both edges
Synchronous
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
FTOD
FTIS
FTCS
FTCWH
FTCWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
PWOD
Scyc
SCKW
SCKr
SCKf
TXD
RXS
RXH
TRGS
RESD
RESOW
Min.

20
20

20
20
1.5
2.5

20
20
1.5
2.5

4
6
0.4



20
20
20

132
Max. Unit
30


30




30




30


0.6
1.5
1.5
30



200

Rev. 3.00, 03/04, page 803 of 830
ns
ns
t
ns
t
ns
t
t
t
ns
ns
ns
t
cyc
cyc
cyc
Scyc
cyc
cyc
Test Conditions
Figure 25.19
Figure 25.20
Figure 25.21
Figure 25.22
Figure 25.24
Figure 25.23
Figure 25.25
Figure 25.26
Figure 25.27
Figure 25.28
Figure 25.29