DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 757

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4.2
The JTAG can be reset in two ways.
• The JTAG is reset when the ETRST pin is held at 0.
• When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while
21.5
The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard
by setting a command in SDIR.
21.5.1
This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS,
SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE).
BYPASS: Instruction code: B'1111
The BYPASS instruction is an instruction that operates the bypass register. This instruction
shortens the shift path to speed up serial data transfer involving other chips on the printed circuit
board. While this instruction is being executed, the test circuit has no effect on the system
circuits.
SAMPLE/PRELOAD: Instruction code: B'0100
The SAMPLE/PRELOAD instruction inputs values from this LSI internal circuitry to the
boundary scan register, outputs values from the scan path, and loads data onto the scan path.
When this instruction is being executed, this LSI's input pin signals are transmitted directly to the
internal circuitry, and internal circuit values are directly output externally from the output pins.
This LSI system circuits are not affected by execution of this instruction.
In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal
circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the
boundary scan register and read from the scan path. Snapshot latching does not affect normal
operation of this LSI.
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan
register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation,
when the EXTEST instruction was executed an undefined value would be output from the output
pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST
instruction, the parallel output latch value is constantly output to the output pin).
ETMS = 1.
JTAG Reset
Boundary Scan
Supported Instructions
Rev. 3.00, 03/04, page 715 of 830