DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 573

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• STR2
Note:
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
3
2
1
0
DBU27
DBU26
DBU25
DBU24
C/D2
DBU22
IBF2
OBF2
*
Only 0 can be written to clear the flag.
All 0
0
0
0
0
R/W
R
R/W
R
R/(W)
*
R/W
R
R
R
R
R
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR2 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR2 contains data or a command.
0: Content of input data register (IDR2) is data
1: Content of input data register (IDR2) is a command
Defined by User
The user can use this bit as necessary.
Input Data Register Full
Indicates whether or not there is receive data in IDR2.
This bit is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR2
[Clearing condition]
When the slave processor reads IDR2
1: There is receive data in IDR2
[Setting condition]
When the host processor writes to IDR2 using I/O
write cycle
Output Data Register Full
Indicates whether or not there is transmit data in
ODR2.
0: There is not transmit data in ODR2
[Clearing condition]
When the host processor reads ODR2 using I/O read
cycle, or the slave processor writes 0 to the OBF2 bit
1: There is transmit data in ODR2
[Setting condition]
When the slave processor writes to ODR2
Rev. 3.00, 03/04, page 531 of 830