DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 568

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.5
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 16.2 shows the initial value of each register. Table 16.3 shows the host register selection in
address match determination. Table 16.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 16.2 LADR1, LADR2 Initial Values
Table 16.3 Host Register Selection
Rev. 3.00, 03/04, page 526 of 830
Register Name
LADR1
LADR2
Bits 15 to 3
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
Bit 2 Bit 1
I/O Address
Initial Value
H'0060
H'0062
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O read
Bit 0
Description
I/O address of channel 1
I/O address of channel 2
Transfer
Cycle
Host Register Selection
IDR1 write (data),
C/D1 ← 0
IDR1 write (command),
C/D1 ← 1
ORD1 read
STR1 read
IDR2 write (data),
C/D2 ← 0
IDR2 write (command),
C/D2 ← 1
ODR2 read
STR2 read