DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 686

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
The procedures for download, initialization, and programming are shown in figure 20.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
Rev. 3.00, 03/04, page 644 of 830
Programming Procedure in User Program Mode
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Set SCO to 1 and
execute download
Start programming
specify download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
parameter
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 20.11 Programming Procedure
1.
2.
3.
4.
5.
6.
7.
8.
No
JSR FTDAR setting + 16
Disable interrupts and bus
Set parameters to ER1
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
master operation
other than CPU
programming is
Programming
Required data
FPFR = 0?
completed?
and ER0
1
Yes
Yes
Clear FKEY and
error processing
No
programming
9.
10.
11.
12.
13.
14.
15.