DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 148

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2
BCR2 is used to specify the access mode for the CP extended area.
Rev. 3.00, 03/04, page 106 of 830
Bit
3
2
1
0
Bit
7, 6
5
4
Bit Name
BRSTS0

IOS1
IOS0
Bit Name

ABWCP
ASTCP
Bus Control Register 2 (BCR2)
Initial
Value
0
0
1
1
Initial
Value
All 0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Valid only in the normal extended mode.
Burst Cycle Select 0
Selects the number of words that can be accessed by burst
access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
Reserved
The initial value should not be changed.
IOS Select 1 and 0
Select the address range where the IOS signal is output.
See table 6.15.
CP Extended Area Bus Width Control
CP Extended Area Access State Control
Description
Reserved
The initial value should not be changed.
Selects the bus width for access to the CP extended area
when the CPCSE bit is set to 1
0: 16-bit bus
1: 8-bit bus
Selects the number of states for access to the CP extended
area when the CPCSE bit is set to 1. This bit also enables or
disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled