DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 99

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
4
3
2
1
0
Bit Name
IICE
FLSHE
—
ICKS1
ICKS0
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
IIC Master Enable
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
1: IIC_1 registers are accessed in an area from
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS,
FTDAR), control registers of power-down states
(SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and
control registers of on-chip peripheral modules
(BCR2, WSCR2, PCSR, SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is reserved.
1: Control registers of flash memory are accessed in
Reserved
The initial value should not be changed.
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, see section 12.3.4, Timer Control
Register (TCR).
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
SCI_2 registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
SCI_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
PWMX registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
IIC_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
Control registers of power-down states and on-
chip peripheral modules are accessed in an area
from H'FFFF80 to H'FFFF87.
an area from H'FFFE88 to H'FFFE8F.
Area from H'FFFF80 to H'FFFF87 is reserved.
Rev. 3.00, 03/04, page 57 of 830