DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 697

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The difference between the erasing procedures in user program mode and user boot mode depends
on whether the MAT is switched or not as shown in figure 20.15.
MAT switching is enabled by writing a specific value to FMATS. However note that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
read is undetermined. Perform MAT switching in accordance with the description in section 20.6,
Switching between User MAT and User Boot MAT.
Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
20.4.4
In the descriptions in the previous section, the programming/erasing procedure programs and
storable areas for program data are assumed to be in the on-chip RAM. However, the program and
the data can be stored in and executed from other areas, such as part of flash memory which is not
to be programmed or erased, or somewhere in the external address space.
(1)
1. The on-chip programming/erasing program is downloaded from the address in the on-chip
2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So,
3. Download by setting the SCO bit to 1 will lead to switching of the MAT. If, therefore, this
4. The flash memory is accessible until the start of programming or erasing, that is, until the
5. The flash memory is not accessible during programming/erasing operations, therefore, the
6. After programming/erasing, the flash memory should be inhibited until FKEY is cleared.
RAM specified by FTDAR, therefore, this area is not available for use.
make sure that this area is secured.
operation is used, it should be executed from the on-chip RAM.
result of downloading has been determined. When in a mode in which the external address
space is not accessible, such as single-chip mode, the required procedure programs, NMI
handling vector and NMI handler should be transferred to the on-chip RAM before
programming/erasing of the flash memory starts.
operation program is downloaded to the on-chip RAM to be executed. The NMI-handling
vector and programs such as that which activate the operation program, and NMI handler
should thus be stored in on-chip memory other than flash memory or the external address
space.
The reset state (RES = 0) must be in place for more than 100 µs when the LSI mode is changed
to reset on completion of a programming/erasing operation.
Conditions that Apply to Programming/Erasing
Procedure Program and Storable Area for Programming Data
Rev. 3.00, 03/04, page 655 of 830