DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 551

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.2
Table 16.1 lists the input and output pins of the LPC.
Table 16.1 Pin Configuration
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
Name
LPC address/
data 3 to 0
LPC frame
LPC reset
LPC clock
Serialized
interrupt request
LSCI general
output
LSMI general
output
PME general
output
GATE A20
LPC clock run
LPC power-down LPCPD
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
Input/Output Pins
input/output function.
external resistor is necessary to pull the signal up to VCC.
Abbreviation
LAD3 to LAD0 PE3 to
LFRAME
LRESET
LCLK
SERIRQ
LSCI
LSMI
PME
GA20
CLKRUN
Port
PE0
PE4
PE5
PE6
PE7
PD0
PD1
PD2
PD3
PD4
PD5
I/O
Input*
Input*
Input
I/O*
Output*
Output*
Output*
Output*
I/O*
Input*
I/O
1
1,
*
1
1
1
2
1,
1,
1,
1,
*
*
*
*
2
2
2
2
Function
Serial (4-signal-line) transfer cycle
type/address/data signals,
synchronized with LCLK
Transfer cycle start and forced
termination signal
LPC interface reset signal
33 MHz PCI clock signal
Serialized host interrupt request
signal, synchronized with LCLK
(SMI, HIRQ1, HIRQ6, HIRQ9 to
HIRQ12)
General output
General output
General output
A20 gate control signal output
LCLK restart request signal in case
of serial host interrupt request
LPC module shutdown signal
Rev. 3.00, 03/04, page 509 of 830

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