DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 265
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.9.2
P9DR stores output data for the port 9 pins.
Note: The initial value of bit 6 is determined in accordance with the P96 pin state.
8.9.3
The relationship between the operating mode, register setting values, and pin functions are as
follows.
• P97/WAIT/CS256
Bit
7
6
5
4
3
2
1
0
Operating
Mode
WMS1,
WMS21
CS256E
P97DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and
the P97DDR bit.
Bit Name
P97DR
P96DR
P95DR
P94DR
P93DR
P92DR
P91DR
P90DR
Port 9 Data Register (P9DR)
Pin Functions
P97 input
pin
0
Initial Value
0
Undefined*
0
0
0
0
0
0
0
P97 output
pin
1
All 0
Extended Mode
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
CS256 output
Description
P9DR stores output data for the port 9 pins that are
used as the general output port except for bit 6.
If a port 9 read is performed while the P9DDR bits are
set to 1, the P9DR values are read. If a port 9 read is
performed while the P9DDR bits are cleared to 0, the
pin states are read.
pin
1
One bit is set as
WAIT input pin
1
Rev. 3.00, 03/04, page 223 of 830
P97 input
Single-Chip Mode
pin
0
P97output
pin
1
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