DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 682

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
(2)
The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
1. Bit rate adjustment
2. Waiting for inquiry set command
3. Automatic erasure of all user MAT and user boot MAT
4. Waiting for programming/erasing command
Note that memory read of the user MAT/user boot MAT can only read the programmed data after
all user MAT/user boot MAT has automatically been erased.
Rev. 3.00, 03/04, page 640 of 830
Bit Rate of Host
4,800 bps
9,600 bps
19,200 bps
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about user-MAT size and configuration, MAT start address, and support state, the
required information is transmitted to the host.
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
 When the program preparation notice is received, the state for waiting program data is
 When the erasure preparation notice is received, the state for waiting erase-block data is
 There are many commands other than programming/erasing. Examples are sum check,
State Transition Diagram
entered. The programming start address and program data must be transmitted following
the programming command. When programming is finished, the programming start address
must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is
returned to the state of programming/erasing command wait.
entered. The erase-block number must be transmitted following the erasing command.
When the erasure is finished, the erase-block number must be set to H'FF and transmitted.
Then the state for waiting erase-block data is returned to the state for waiting
programming/erasing command. The erasure must be used when the specified block is
programmed without a reset start after programming is executed in boot mode. When
programming can be executed by only one operation, all blocks are erased before the state
for waiting programming/erasing/other command is entered. The erasing operation is not
required.
blank check (erasure check), and memory read of the user MAT/user boot MAT and
acquisition of current status information.
System Clock Frequency
5 to 33 MHz
5 to 33 MHz
8 to 33 MHz