DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 517

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
15.14
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
No
No
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Set ACKB = 1 in ICSR
Master receive mode
Set TRS = 0 in ICCR
Set WAIT = 0 in ICMR
Set TRS = 1 in ICCR
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
Read ICDR
(receiving a single byte) (WAIT = 1)
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
[1] Select receive mode.
[2] Start receiving. The first read
[3] Wait for a receive wait
[7] Set acknowledge data for
[9] Set TRS for stop condition issuance
[14] Clear IRIC.
[12] Wait for 1 byte to be received.
[15] Clear wait mode.
[16] Read the last receive data
[17] Generate stop condition
(Set IRIC at the rise of the 9th clock)
is a dummy read.
(Set IRIC at the fall of the 8 th clock)
(to end the wait insertion)
the last reception.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
Rev. 3.00, 03/04, page 475 of 830