DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 471

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the
operation mode, and selects the generating polynomial.
CRC Data Input Register (CRCDIR): CRCDIR is an 8-bit readable/writable register, to which
the bytes to be CRC-operated are written. The result is obtained in CRCDOR.
CRC Data Output Register (CRCDOR): CRCDOR is a 16-bit readable/writable register that
contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR
after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to
which CRC operation is to be performed, the CRC operation result will be H'0000 if the data
contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1,
respectively, the lower byte of this register contains the result.
Bit
7
6 to 3 
2
1
0
Bit Name
DORCLR
LMS
G1
G0
Initial Value
0
All 0
0
0
0
R/W Description
W
R
R/W CRC Operation Switch
R/W
R/W
CRCDOR Clear
Setting this bit to 1 clears CRCDOR to H
Reserved
The initial value should not be changed.
Selects CRC code generation for LSB-first or MSB-
first communication.
0: Performs CRC operation for LSB-first
1: Performs CRC operation for MSB-first
CRC Generating Polynomial Select
These bits select the polynomial.
00: Reserved
01: X
10: X
11: X
communication. The lower byte (bits 7 to 0) is first
transmitted when CRCDOR contents (CRC code)
are divided into two bytes to be transmitted in two
parts.
communication. The upper byte (bits 15 to 8) is
first transmitted when CRCDOR contents (CRC
code) are divided into two bytes to be transmitted
in two parts.
8
16
16
+ X
+ X
+ X
2
15
12
+ X + 1
+ X
+ X
2
5
+ 1
+ 1
Rev. 3.00, 03/04, page 429 of 830
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0000.