DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 629

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6
16.6.1
The LPC operation stop or enable can be specified by the module stop control register. With the
initial value, LPC operation will stop. Releasing module stop mode enables access to the register.
For details see section 23, Power-Down Modes.
16.6.2
The LPC interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR is required to avoid data
contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the right to access TWR1 to TWR15
has been obtained.
Table 16.13 shows the host address example of registers LADR3, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Usage Notes
Module Stop Setting
Usage Note of LPC Interface
Rev. 3.00, 03/04, page 587 of 830