DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 382

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.3
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 13.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
13.3.1
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared
to 0.
13.3.2
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Rev. 3.00, 03/04, page 340 of 830
Bit
7
6
Bit Name Initial Value R/W
OVF
WT/IT
Register Descriptions
Timer Counter (TCNT)
Timer Control/Status Register (TCSR)
0
0
R/(W)* Overflow Flag
R/W
Description
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
[Clearing conditions]
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
When TCSR is read when OVF = 1, then 0 is written
to OVF
When 0 is written to TME

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