DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 547

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. Note on ACKE and TRS bits in slave mode
15. Notes on Arbitration Lost in Master Mode Operation
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition and address are transmitted from the
master device in slave transmit mode (TRS = 1), the ICDRE flag is set, and 1 is received as the
acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source
even when the address does not match.
To use the I
 When having received 1 as the acknowledge bit value for the last transmit data at the end
 Set receive mode (TRS = 0) before the next start condition is input in slave mode.
The I
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I
figure 15.35.)
In multi-master mode, a bus conflict could happen. When the I
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
Complete transmit operation by the procedure shown in figure 15.23, in order to switch
from slave transmit mode to slave receive mode.
2
C bus interface recognizes the data in transmit/receive frame as an address when
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
2
C bus interface module in slave mode, be sure to follow the procedures below.
2
C bus interface erroneously recognizes that the address call has occurred. (See
Rev. 3.00, 03/04, page 505 of 830
2
C bus interface is operated in