DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 21

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 I
15.1 Features............................................................................................................................. 435
15.2 Input/Output Pins .............................................................................................................. 438
15.3 Register Descriptions ........................................................................................................ 439
15.4 Operation .......................................................................................................................... 465
15.5 Interrupt Source ................................................................................................................ 494
15.6 Usage Notes ...................................................................................................................... 495
Section 16 LPC Interface (LPC) ........................................................................507
16.1 Features............................................................................................................................. 507
16.2 Input/Output Pins .............................................................................................................. 509
16.3 Register Descriptions ........................................................................................................ 510
14.11.1 Features................................................................................................................ 428
14.11.2 Register Descriptions........................................................................................... 428
14.11.3 CRC Operation Circuit Operation........................................................................ 430
14.11.4 Note on CRC Operation Circuit........................................................................... 433
15.3.1 I
15.3.2 Slave Address Register (SAR)............................................................................. 440
15.3.3 Second Slave Address Register (SARX) ............................................................. 441
15.3.4 I
15.3.5 I
15.3.6 I
15.3.7 I
15.3.8 I
15.3.9 I
15.4.1 I
15.4.2 Initialization ......................................................................................................... 467
15.4.3 Master Transmit Operation .................................................................................. 467
15.4.4 Master Receive Operation.................................................................................... 471
15.4.5 Slave Receive Operation...................................................................................... 478
15.4.6 Slave Transmit Operation .................................................................................... 485
15.4.7 IRIC Setting Timing and SCL Control ................................................................ 488
15.4.8 Operation Using the DTC .................................................................................... 490
15.4.9 Noise Canceler..................................................................................................... 492
15.4.10 Initialization of Internal State .............................................................................. 492
16.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 512
16.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 518
16.3.3 Host Interface Control Register 4 (HICR4) ......................................................... 521
16.3.4 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................ 522
16.3.5 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L).................... 526
16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 527
16.3.7 Output Data Registers 0 to 3 (ODR1 to ODR3) .................................................. 527
2
2
2
2
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 439
C Bus Mode Register (ICMR)........................................................................... 442
C Bus Transfer Rate Select Register (IICX3).................................................... 443
C Bus Control Register (ICCR)......................................................................... 446
C Bus Status Register (ICSR)............................................................................ 455
C Bus Extended Control Register (ICXR)......................................................... 459
C SMBus Control Register (ICSMBCR)........................................................... 463
C Bus Data Format ............................................................................................ 465
C Bus Interface (IIC) .....................................................................435
Rev. 3.00, 03/04, page xix of xl