DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 147

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3
The following registers are provided for the bus controller. For the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR). For system control register 2
(SYSCR2), see section 8.6.4, System Control Register 2 (SYSCR2).
• Bus control register (BCR)
• Bus control register 2 (BCR2)
• Wait state control register (WSCR)
• Wait state control register 2 (WSCR2)
6.3.1
BCR is used to specify the access mode for the external address space and the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit
7
6
5
4
Bit Name

ICIS
BRSTRM
BRSTS1
Register Descriptions
Bus Control Register (BCR)
Initial
Value
1
1
0
1
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The initial value should not be changed.
Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle cycle
between successive external read and external write cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
Valid only in the normal extended mode.
Burst ROM Enable
Selects the bus interface for the external address space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, burst ROM interface cannot be selected for the
256 -kbyte extended area and CP extended area.
Valid only in the normal extended mode.
Burst Cycle Select 1
Selects the number of states in the burst cycle of the burst
ROM interface.
0: 1 state
1: 2 states
Rev. 3.00, 03/04, page 105 of 830