DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 510

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 15.7 shows the sample flowchart for the operations in master transmit mode.
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR (ICDRT) write operations, are described below.
Rev. 3.00, 03/04, page 468 of 830
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode
No
No
No
No
No
Write transmit data in ICDR
Write transmit data in ICDR
Read BBSY in ICCR
Read ACKB in ICSR
Read ACKB in ICSR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Yes
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Set BBSY =1 and
Set BBSY = 0 and
Set MST = 1 and
End of transmission?
TRS = 1 in ICCR
SCP = 0 in ICCR
SCP = 0 in ICCR
Transmit mode?
Initialize IIC
ACKB = 0?
BBSY = 0?
(ACKB = 1?)
IRIC = 1?
IRIC = 1?
IRIC = 1?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
[9] Set transmit data for the second and
[10] Wait for 1 byte to be transmitted.
[11] Determine end of transfer
[12] Stop condition issuance
(slave address + R/W).
(After writing to ICDR, clear IRIC
continuously.)
transferred from the slave device.
subsequent bytes.
immediately.)
(After writing to ICDR, clear IRIC
Master receive mode