DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 184

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(c) Pin Auto-Wait Mode: A specified number of wait states T
and T
of φ in the last T
WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low,
T
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.25 shows an example of wait state insertion timing in pin wait mode.
The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input
disabled.
Rev. 3.00, 03/04, page 142 of 830
W
states are inserted only up to the specified number of states.
3
state when accessing the external address space if the WAIT pin is low at the falling edge
Read
Write
CPCS1 (CPCSE = 1)
Figure 6.25 Example of Wait State Insertion Timing (Pin Wait Mode)
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
* For external address space access, this signal is not output when the 256-kbyte expansion area
AS (IOSE = 0)
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
*
IOS (IOSE = 1)
2
state. The number of wait states T
Address bus
Data bus
Data bus
φ
WAIT
WR
RD
T
1
By program wait
T
2
W
T
W
is specified by the settings of the WC1 and
Write data
T
By WAIT pin
W
W
are inserted between the T
T
W
Read data
T
3
2
state

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