DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 452

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.7.5
Before starting transmitting and receiving data, initialize the SCI using the following procedure.
Initialization is also necessary before switching from transmission to reception and vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ORER, ERS, and PER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set
4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and
7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval.
To switch from reception to transmission, first verify that reception has completed, and initialize
the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception
completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from
transmission to reception, first verify that transmission has completed, and initialize the SCI. At
Rev. 3.00, 03/04, page 410 of 830
Figure 14.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock
the PE bit to 1.
TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high
impedance state.
TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output
clock pulses.
Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.
Synchronization
sampling timing
Data sampling
timing
Initialization
Receive data
(RxD)
Internal
basic clock
0
186 clock
cycles
372 clock cycles
Frequency is 372 Times the Bit Rate)
185
Start bit
371
0
D0
185
371 0
D1