DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 773

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit Bit Name
6
5
4
3
2
1
LSON
NESEL
EXCLE

PNCCS
PNCAH
Initial
Value
0
0
0
0
0
0
R/W Description
R/W Low-Speed On Flag
R/W Noise Elimination Sampling Frequency Select
R/W Subclock Input Enable
R/W Reserved
R/W Address Multiplex Chip Select
R/W Address Multiplex Address Hold
Specifies the operating mode to be entered after executing the
SLEEP instruction. This bit also controls whether to shift to high-
speed mode or subactive mode when watch mode is cancelled.
When the SLEEP instruction is executed in high-speed mode or
medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
Selects the frequency by which the subclock (φSUB) input from
the EXCL pin is sampled using the clock (φ) generated by the
system clock pulse generator.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
The initial value should not be changed.
Controls the output polarity of chip select signals (CS256, CPCS,
IOS) in the address multiplex extended mode.
0: Outputs CS256, CPCS, and IOS
1: Outputs CS256, CPCS, and IOS
Controls the output polarity of the address hold signal (AH) in the
address multiplex extended mode.
0: Outputs AH
1: Outputs AH
Rev. 3.00, 03/04, page 731 of 830