DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 863

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
Section 5 Interrupt
Controller
5.7.4 Note on IRQ Status
Registers (ISR16, ISR)
Section 12 8-bit Timer
12.1 Features
Section 12.3.4 Timer
Control register (TCR)
Table 12.2 Clock Input to
TCNT and Count
Condition
Main Revisions and Additions in this Edition
Page
100
305
312,
313
Revisions (See Manual for Details)
Section 5.7.4 added.
• Cascading of TMR_0 and TMR_1
Description amended.
Note: * If the TMR_0 clock input is set as the TCNT_1
Channel CKS2 CKS1 CKS0 Description
TMR_Y
TMR_X
(Cascading of TMR_Y and TMR_X is not allowed)
 Operation as a 16-bit timer can be performed using
TMR_0 as the upper half and TMR_1 as the lower half
(16-bit count mode). TMR_1 can be used to count
TMR_0 compare-match occurrences (compare match
count mode)
overflow signal and the TMR_1 clock input is set as
the TCNT_0 compare-match signal simultaneously,
a count-up clock cannot be generated. Setting of
these conditions should therefore be avoided.
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
TCR
0
1
0
1
0
0
1
0
1
0
Rev. 3.00, 03/04, page 821 of 830
Disables clock input
Increments at falling edge
of internal clock φ/4
Increments at falling edge
of internal clock φ/256
Increments at falling edge
of internal clock φ/2048
Setting prohibited
Disables clock input
Increments at falling edge
of internal clock φ
Increments at falling edge
of internal clock φ/2
Increments at falling edge
of internal clock φ/4
Setting prohibited