DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 689

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8. The return value in the initialization program, FPFR (general register R0L) is determined.
9. All interrupts and the use of a bus master other than the CPU are prohibited.
10. FKEY must be set to H′5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
MOV.L
JSR
NOP
 The general registers other than R0L are held in the initialization program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the initialization program, 128-byte stack area at the
 Interrupts can be accepted during the execution of the initialization program. The program
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, the
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts and bus mastership to other than the CPU, such as to the DTC, are
prohibited.
To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to
B'1 in interrupt control mode 0 or bits 7 and 6 (I and UI) should be set to B'11 in interrupt
control mode 1. Interrupts other than NMI are held and not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to other than the CPU, such as to the DTC, the error
protection state is entered. Therefore, taking bus mastership by the DTC is prohibited.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
 Example of the FMPAR setting
maximum must be allocated in RAM.
storage area and stack area in the on-chip RAM and register values must not be destroyed.
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits of the address must be H'00 or H'80 as the
boundary of 128 bytes.
#DLTOP+32,ER2
@ER2
; Set entry address to ER2
; Call initialization routine
Rev. 3.00, 03/04, page 647 of 830