DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 439

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

No
No
No
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (1)
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Set MPIE bit in SCR to 1
Read RDRF flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
All data received?
FER ∨ ORER = 1
This station’s ID?
FER ∨ ORER = 1
Start reception
Initialization
RDRF = 1
RDRF = 1
<End>
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Error processing
[3]
[1]
[2]
(Continued on
next page)
[4]
[5]
[1] SCI initialization:
[2] ID reception cycle:
[3] SCI status check, ID reception and
[4] SCI status check and data reception:
[5] Receive error processing and break
Legend
∨ : Logical add (OR)
The RxD pin is automatically designated
as the receive data input pin.
Set the MPIE bit in SCR to 1.
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Rev. 3.00, 03/04, page 397 of 830