DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 555

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
Bit Name Initial Value Slave Host Description
FGA20E
SDWNE
0
0
R/W
R/W
R/W
Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate
can be implemented by firmware operation of the
PD3 output.
When the fast A20 gate function is enabled, the DDR
bit for PD3 must not be set to 1.
0: Fast A20 gate function disabled
1: Fast A20 gate function enabled
LPC Software Shutdown Enable
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of
initialization by an LPC reset and an LPC shutdown,
see section 16.4.6, LPC Interface Shutdown
Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
1: LPC hardware shutdown state setting enabled
[Setting condition]
Other function of the pin is enabled
GA20 output internal state is initialized to 1
GA20 pin output is open-drain (external VCC
pull-up resistor required)
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown release (rising edge of
LPCPD signal)
Hardware shutdown state when LPCPD signal is
low
Writing 1 after reading SDWNE = 0
Rev. 3.00, 03/04, page 513 of 830

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