DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 688

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4. FKEY is cleared to H'00 for protection.
5. The value of the DPFR parameter must be checked and the download result must be
6. The operating frequency are set to the FPEFEQ parameters for initialization.
7. Initialization
Rev. 3.00, 03/04, page 646 of 830
 In the download processing, any interrupts are not accepted. However, interrupt requests
 When the level-detection interrupt requests are to be held, interrupts must be input until the
 When hardware standby mode is entered during download processing, the normal
 Since a stack area of 128 bytes at the maximum is used, the area must be allocated before
 If a flash memory access by the DTC signal is requested during downloading, the operation
confirmed.
 Check the value of the DPFR parameter (one byte of start address of the download
 If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
 If the value of the DPFR parameter is different from before downloading, check the SS bit
 The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the start
address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and
initialization is executed by using the following steps.
are held. Therefore, when the user procedure program is returned, the interrupts occur.
download is ended.
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
setting the SCO bit to 1.
cannot be guaranteed. Therefore, an access request by the DTC signal must not be
generated.
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
ER0).
The settable range of the FPEFEQ parameter is 5 to 33 MHz. When the frequency is set to
out of this range, an error is returned to the FPFR parameter of the initialization program
and initialization is not performed. For details on the frequency setting, see the description
in 20.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ).