DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 453

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission
completion can be verified by reading the TEND flag.
14.7.6
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data is
re-transmitted. Figure 14.29 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this
Figure 14.31 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DTC. In transmission, the
TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request
when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of
transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand.
The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error
occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains
as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the
specified number of bytes, including re-transmission in the case of error occurrence. However, the
ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE
bit to 1 to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable it prior to making SCI
settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
re-transferred from TDR to TSR allowing automatic data retransmission.
case, one frame of data is determined to have been transmitted including re-transfer, and the
TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is
set to 1. Writing transmit data to TDR starts transmission of the next data.
Serial Data Transmission (Except in Block Transfer Mode)
Rev. 3.00, 03/04, page 411 of 830