DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 451

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
14.7.3
Block transfer mode is different from normal smart card interface mode in the following respects.
• If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
• Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5
• Although the ERS flag in block transfer mode displays the error signal status as in normal
14.7.4
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a basic
clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0
settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 14.28. The reception margin here is determined by the following formula.
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
is set by error detection, clear the bit before receiving the parity bit of the next frame.
before the start of the next frame.
etu after transmission start.
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
M =  (0.5 –
M = (0.5 – 1/2 x 372) x 100 [%] = 49.866%
Block Transfer Mode
Receive Data Sampling Timing and Reception Margin
M:
N:
D:
L:
F:
Reception margin (%)
Ratio of bit rate to clock (N = 32, 64, 372, 256)
Clock duty (D = 0 to 1.0)
Frame length (L = 10)
Absolute value of clock rate deviation
2N
1
) – (L – 0.5) F –
 D – 0.5 
N
(1 + F)  × 100 [%]
Rev. 3.00, 03/04, page 409 of 830
... Formula (1)