DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 190

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8
6.8.1
The BSC has a bus arbiter that arbitrates bus master operations. There are two bus masters – the
CPU and DTC – that perform read/write operations while they have bus mastership.
6.8.2
Each bus master requests the bus mastership by means of a bus mastership request signal. The bus
arbiter detects the bus mastership request signal from the bus masters, and if a bus request occurs,
it sends a bus mastership request acknowledge signal to the bus master that made the request at the
designated timing. If there are bus requests from more than one bus master, the bus mastership
request acknowledge signal is sent to the one with the highest priority. When a bus master receives
the bus mastership request acknowledge signal, it takes the bus mastership until that signal is
canceled. The order of bus master priority is as follows:
6.8.3
When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus mastership and is currently operating, the bus mastership is not
necessarily transferred immediately. Each bus master can relinquish the bus mastership at the
timings given below.
CPU: The CPU is the lowest-priority bus master, and if a bus mastership request is received from
the DTC, the bus arbiter transfers the bus mastership to the DTC. The timing for transferring the
bus mastership is as follows:
• Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
• If the CPU is in sleep mode, it transfers the bus mastership immediately.
DTC: The DTC sends the bus arbiter a request for the bus mastership when a request for DTC
activation occurs. The DTC releases the bus mastership after a series of processes has completed.
Rev. 3.00, 03/04, page 148 of 830
in discrete operations, as in the case of a long-word size access, the bus is not transferred at a
break between the operations. For details see section 2.7, Bus States During Instruction
Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual.
(High) DTC > CPU (Low)
Bus Arbitration
Overview
Operation
Bus Mastership Transfer Timing