DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 362

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.3.9
TISR selects a signal source of external clock/reset input for the counter.
12.3.10 Timer Connection Register I (TCONRI)
TCONRI controls TMR_X input capture.
Rev. 3.00, 03/04, page 320 of 830
Bit
7 to 1
0
Bit
7 to 5
4
3 to 0
Timer Input Select Register (TISR)
Bit Name
Bit Name Initial Value R/W
ICST
IS
All 1
0
Initial Value
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The initial values should not be modified.
Input Select
Selects TMIY or ExTMIY as the signal source of
external clock/reset input for the TMR_Y counter.
When external reset input is selected for the CCLR0
and CCLR1 in TCR_Y or external clock is selected
for the CKS2 to CKS0 in TCR_Y, set this bit to1.
0: TMIY or ExTMIY (TMCIY/TMRIY) is not selected
1: TMIY or ExTMIY (TMCIY/TMRIY) is selected
Description
Reserved
The initial values should not be modified.
Input Capture Start Bit
TMR_X has input capture registers (TICR,
TICRR, and TICRF). TICRR and TICRF can
measure the width of a pulse by means of a
single capture operation under the control of the
ICST bit. When a rising edge followed by a falling
edge is detected on TMRIX after the ICST bit is
set to 1, the contents of TCNT at those points are
captured into TICRR and TICRF, respectively,
and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Reserved
The initial values should not be modified.

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