DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 741

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21.2
Table 21.1 shows the JTAG pin configuration.
Table 21.1 Pin Configuration
Pin Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Input/Output Pins
Abbreviation
ETCK
ETMS
ETDI
ETDO
ETRST
Input
Input
I/O
Input
Output
Input
Function
Test clock input
Provides an independent clock supply to the
JTAG. As the clock input to the ETCK pin is
supplied directly to the JTAG, a clock waveform
with a duty cycle close to 50% should be input.
For details, see section 25, Electrical
Characteristics. If there is no input, the ETCK pin
is fixed to 1 by an internal pull-up.
Test mode select input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP
controller. If there is no input, the ETMS pin is
fixed to 1 by an internal pull-up.
Serial data input
Performs serial input of instructions and data for
JTAG registers. ETDI is sampled on the rise of
the ETCK pin. If there is no input, the ETDI pin is
fixed to 1 by an internal pull-up.
Serial data output
Performs serial output of instructions and data
from JTAG registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the high-
impedance state.
Test reset input signal
Initializes the JTAG asynchronously. If there is
no input, the ETRST pin is fixed to 1 by an
internal pull-up.
Rev. 3.00, 03/04, page 699 of 830

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