DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 665

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
3
2, 1
0
Bit Name
WEINTE

SCO
Initial
Value
0
All 0
0
R/W
R/W
R/W
(R)/W*
Description
Program/Erase Enable
Modifies the space for the interrupt vector table, when
interrupt vector data is not read successfully during
programming/erasing flash memory or switching between
a user MAT and a user boot MAT. When this bit is set to
1, interrupt vector data is read from address spaces
H'FFE080 to H'FFE0FF (on-chip RAM space), instead of
from address spaces H'000000 to H'00007F (up to vector
number 31). Therefore, make sure to set the vector table
in the on-chip RAM space before setting this bit to 1.
The interrupt exception handling on and after vector
number 32 should not be used because the correct
vector is not read, resulting in the CPU runaway.
0: The space for the interrupt vector table is not
1: The space for the interrupt vector table is modified.
Reserved
The initial value should not be changed.
Source Program Copy Operation
Requests the on-chip programming/erasing program to
be downloaded to the on-chip RAM.
When this bit is set to 1, the on-chip program which is
selected by FPCS/FECS is automatically downloaded in
the on-chip RAM specified by FTDAR.
In order to set this bit to 1, H′A5 must be written to FKEY
and this operation must be executed in the on-chip RAM.
Four NOP instructions must be executed immediately
after setting this bit to 1.
Since this bit is cleared to 0 when download is
completed, this bit cannot be read as 1.
All interrupts must be disabled. This should be made in
the user system.
0: Download of the on-chip programming/erasing
program to the on-chip RAM is not executed.
modified.
When interrupt vector data is not read successfully,
the operation for the interrupt exception handling
cannot be guaranteed. An occurrence of any
interrupts should be masked.
Even when interrupt vector data is not read
successfully, the interrupt exception handling up to
vector number 31 is enabled.
Rev. 3.00, 03/04, page 623 of 830