DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 38

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 5.8
Table 5.9
Section 6 Bus Controller (BSC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.9
Table 6.10
Table 6.11
Table 6.12
Table 6.13
Table 6.14
Table 6.15
Table 6.16
Table 6.17
Section 7 Data Transfer Controller (DTC)
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Section 8 I/O Ports
Table 8.1
Table 8.1
Table 8.1
Rev. 3.00, 03/04, page xxxvi of xl
Number of States in Interrupt Handling Routine Execution Status ........................ 96
Interrupt Source Selection and Clearing Control .................................................... 98
Pin Configuration.................................................................................................. 104
Address Ranges and External Address Spaces ..................................................... 113
Bit Settings and Bus Specifications of Basic Bus Interface.................................. 114
Bus Specifications for Basic Extended Area/Basic Bus Interface ........................ 115
Bus Specifications for 256-kbyte Extended Area/Basic Bus Interface................. 116
Bus Specifications for CP Extended Area (Basic Mode)/Basic Bus Interface ..... 117
Address-Data Multiplex Address Spaces.............................................................. 119
Bit Settings and Bus Specifications of Basic Bus Interface.................................. 120
Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Address Cycle) .................................................................................................... 120
Bus Specifications for IOS Extended Area/Multiplex Bus Interface
Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
Bus Specifications for CP Extended Area/Multiplex Bus Interface
Bus Specifications for CP Extended Area/Multiplex Bus Interface
Address Range for IOS Signal Output.................................................................. 123
Data Buses Used and Valid Strobes...................................................................... 126
Pin States in Idle Cycle......................................................................................... 147
Correspondence between Interrupt Sources and DTCER ..................................... 155
DTC Event Counter Conditions............................................................................ 159
Flag Status/Address Code..................................................................................... 160
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 163
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) .... 164
Register Functions in Normal Mode..................................................................... 166
Register Functions in Repeat Mode...................................................................... 167
Register Functions in Block Transfer Mode ......................................................... 168
DTC Execution Status .......................................................................................... 171
Number of States Required for Each Execution Status ........................................ 172
Port Functions....................................................................................................... 177
Port Functions (cont) ............................................................................................ 178
Port Functions (cont) ............................................................................................ 179
(Data Cycle) ......................................................................................................... 120
(Address Cycle).................................................................................................... 121
(Data Cycle) ......................................................................................................... 121
(Address Cycle).................................................................................................... 121
(Data Cycle) ......................................................................................................... 122