DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 166

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5
The normal extended bus interface enables direct connection to ROM and SRAM. For details on
selection of the bus specifications for the basic extended area, 256-kbyte extended area, and CP
extended area, see tables 6.4 to 6.6.
The address-data multiplex extended bus interface enables direct connection to products that
supports this bus interface. For details on selection of the bus specifications for the IOS extended
area, 256-kbyte extended area, and CP extended area, see tables 6.9 to 6.14.
6.5.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or
lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed,
according to the bus specifications for the area being accessed (8-bit access space or 16-bit access
space) and the data size.
(1) 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space.
With the 8-bit access space, the upper data bus (D15 to D8/AD15 to AD8) is always used for
accesses. The amount of data that can be accessed at one time is one byte: a word access is
performed as two byte accesses, and a longword access, as four byte accesses.
Rev. 3.00, 03/04, page 124 of 830
Bus Interface
Data Size and Data Alignment
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
15
31
23
15
D15
7
7
7
Upper data bus
D8 D7
24
16
0
8
0
8
0
Lower data bus
D0