DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 789

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.10
Module stop mode can be individually set for each on-chip peripheral module.
When the corresponding MSTP bit in MSTPCR and SUBMSTP is set to 1, module operation
stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the
corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation
resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral
modules other than the PWM, PWMX, A/D converter, and part of the SCI are retained.
After the reset state is cancelled, all modules other than DTC are in module stop mode.
While an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
23.11
The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a
direct transition is made from high-speed mode to subactive mode, there is no interruption of
program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and
then executing the SLEEP instruction. After a transition, direct transition exception handling
starts.
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set
to 11, and the PSS bit in TCSR (WDT_1) set to 1.
To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in
SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in
SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TCSR
(WDT_1) set to 1.
Module Stop Mode
Direct Transitions
Rev. 3.00, 03/04, page 747 of 830