MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1049
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
DCP Channel 2 is controlled by a variable sized command structure. This register points
to the command structure to be executed.
EXAMPLE
Address:
Re-
13.3.25 DCP Channel 2 Semaphore Register (HW_DCP_CH2SEMA)
The DCP Channel 2 semaphore register is used to synchronize the CPU instruction stream
and the DMA chain processing state. After a command chain has been generated in memory,
software should write the address of the first command descriptor to the CMDPTR register
and then write a non-zero value to the semaphore register to indicate that the channel is
active. Each command packet has a chaining bit which indicates that another descriptor
should be loaded into the channel upon completion of the current descriptor. If the chaining
bit is not set, the next address will not be loaded into the CMDPTR register. Each packet
also contains a decrement semaphore bit, which indicates that the counting semaphore
should be decremented after the operation. A channel is considered active when the
semaphore is a non-zero value. When programming a series operations, software must
properly program the semaphore values in conjunction with the decrement_semaphore bits
in the control packets to ensure that the proper number of descriptors are activated. A
semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR
register. The logic will also clear the semaphore if an error has occurred.
Freescale Semiconductor, Inc.
set
Bit
W
pointer
R
31
0
ADDR
Field
31 0
30
0
29
0
pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(2);
HW_DCP_CHn_CMDPTR_WR(2, v);
HW_DCP_CH2CMDPTR
28
0
Pointer to descriptor structure to be processed for channel 2.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_DCP_CH2CMDPTR field descriptions
23
0
22
0
8002_8000h base + 180h offset = 8002_8180h
21
0
20
0
19
0
18
0
// Write channel 2 command pointer
17
0
ADDR
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
Chapter 13 Data Co-Processor (DCP)
0
9
0
8
// Read current command
0
7
0
6
0
5
0
4
3
0
0
2
0
1
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