MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1064
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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EMI Clocking
14.2.3 Memory Mapping to Address Space
The following figures provide examples of address space mapping from a 32-bit bus address
to DRAM address fields. The first example corresponds to a memory device with 8 banks,
13 row bits, and 10 column bits. The second example corresponds to a memory device with
8 banks, 14 row bits, and 10 column bits.
14.3 EMI Clocking
The EMI uses an external clock input from the ASIC device. Considering the design speed
and complexity, this design may not be able to adhere to the skew and delay requirements
of a PLL-based clocking scheme. As an alternative, this EMI uses a clocking system that
propagates a clock from the memory controller to the memory devices. The largest challenge
with this clock forwarding scheme is the management of the clock skew for the round-trip
data transfer.
14.3.1 General System Behavior
In this system, the command and address for the transaction are sent from the memory
controller coincident with the falling edge of the memory controller clock. Because the
clock, command, and address signals all have roughly the same pad and flight delays to
travel to the memory, the rising edge of the clock at the memory is centered with the
command and address signals, allowing reliable capture. In addition, because all signals
are sourced from the same location, this clocking system can tolerate a significant skew
and provides more flexibility in timing.
14.3.2 Changing Input Clock Frequency
The operating frequency of the EMI is dependent on an ASIC-level input clock. There are
situations in which the user may wish to modify the frequency of the clock without resetting
the memory controller. To change the clock frequency at which the EMI operates, the
1064
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
dont care
dont care
Figure 14-2. Memory Address Mapping Example 1
Figure 14-3. Memory Address Mapping Example 2
[31:29]
[31:28]
chip-select
chip-select
[28]
[27]
[27:14]
[26:14]
row
row
[13:11]
[13:11]
bank
bank
column
column
[10:1]
[10:1]
datapath
datapath
[0]
[0]
Freescale Semiconductor, Inc.
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