MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 860

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
860
Reset
EN_USB_CLKS
CLKGATEEMI
Bit
LFR_SEL
W
RSRVD6
RSRVD5
RSRVD4
DIV_SEL
RSRVD3
R
CP_SEL
POWER
29 28
27 26
25 24
23 22
21 20
Field
31
30
19
18
17
15
0
14
0
TEST MODE FOR FREESCALE USE ONLY.
Always set to zero (0).
TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor.
0x0
0x1
0x2
0x3
Always set to zero (0).
TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current
0x0
0x1
0x2
0x3
Always set to zero (0).
TEST MODE FOR FREESCALE USE ONLY. This field is currently NOT supported.
0x0
0x1
0x2
0x3
Always set to zero (0).
0: 8-phase PLL outputs for USB1 PHY are powered down. If set to 1, 8-phase PLL outputs for USB1 PHY
are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI1 phy to enable USB1
operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB1 is set, this bit will be set automatically
when USB0 remote wakeup event happens.
PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL1 on before using the PLL1 as a
clock source. This is the time the PLL1 takes to lock to 480 MHz. If
HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM1 is set, this bit will be set to one (1'b1) automatically
when USB1 remote wakeup event happens. Note: The HW_CLKCTRL_PLL0CTRL0_POWER bit must be
set to on to ungate the reference xtal to all of the PLLs.
13
0
DEFAULT — Default loop filter resistor
TIMES_2 — Doubles the loop filter resistor
TIMES_05 — Halves the loop filter resistor
UNDEFINED — Undefined
DEFAULT — Default charge pump current
TIMES_2 — Doubles charge pump current
TIMES_05 — Halves the charge pump current
UNDEFINED — Undefined
DEFAULT — PLL1 frequency is 480 Mhz
LOWER — Lower the PLL1 fequency from 480MHz to 384Mhz
LOWEST — Lower the PLL1 fequency from 480MHz to 288MHz
UNDEFINED — Undefined
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_PLL1CTRL0 field descriptions
12
0
11
0
10
0
0
9
RSRVD1[15:0]
0
8
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0