MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1347
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Freescale Semiconductor, Inc.
RESP_TIMEOUT
CARD_DETECT
TIMEOUT_STAT
FIFO_OVRFLW
SD_PRESENT
RESP_CRC_
DMABURST
DMASENSE
DATA_CRC_
RESP_ERR
DMATERM
SDIO_IRQ
PRESENT
TIMEOUT
DMAREQ
DMAEND
RSVD4
RSVD3
RECV_
RSVD2
27 23
Field
ERR
ERR
31
30
29
28
22
21
20
19
18
17
16
15
14
13
12
11
10
9
SSP Present Bit. 0: SSP is not present in this product. 1: SSP is present.
Reserved
SD/MMC Controller Present bit. 0: SD/MMC controller is not present in this product. 1: SD/MMC controller
is present.
Reflects the state of the SSP_DETECT input pin.
Reserved
Reflects the state of the ssp_dmaburst output port.
Reflects the state of the ssp_dmasense output port. It indicates a DMA error (Timeout or CRC) when asserted
high at the end of a DMA command.
Reflects the state of the ssp_dmaterm output port. This is a toggle signal.
Reflects the state of the ssp_dmareq output port. This is a toggle signal.
Reflects the state of the ssp_dmaend output port. This is a toggle signal.
SDIO IRQ has been detected.
SD/MMC Response failed CRC check. This bit is cleared with soft reset or the rising edge of
HW_SSP_CTRL0_RUN.
SD/MMC Card Responsed to Command with an Error Condition. This bit is cleared with soft reset or the
rising edge of HW_SSP_CTRL0_RUN.
SD/MMC Card Expected Command Response not received within 64 CLK cycles. This indicates a card
error, bad command, or command that failed CRC check. This bit is cleared with soft reset or the rising edge
of HW_SSP_CTRL0_RUN.
Data CRC Error. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN.
SD/MMC - timeout counter expired before data bus was ready. This bit is cleared with soft reset or the rising
edge of HW_SSP_CTRL0_RUN.
Raw Receive Timeout Status. Indicates that no read has occurred to non-empty receive data FIFO for 128
cycles
Reserved
FIFO Overflow Interrupt.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SSP_STATUS field descriptions
Description
Chapter 17 Synchronous Serial Ports (SSP)
1347
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