MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 498

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
AHB-to-APBX Bridge Overview
The DMA controller uses the APBX bus to transfer read and write data to and from each
peripheral. There is no separate DMA bus for these devices. Contention between the DMA's
use of the APBX bus and AHB-to-APB bridge functions' use of the APBX is mediated by
an internal arbitration logic. For contention between these two units, the DMA is favored
and the AHB slave will report not ready through its HREADY output until the bridge transfer
completes. The arbiter tracks repeated lockouts and inverts the priority, so that the CPU is
guaranteed every fourth transfer on the APB.
498
Figure 7-1. AHB-to-APBX Bridge DMA Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SPDIF Transmit
AUART3 RX
AUART3 TX
SAIF1
SAIF2
SAIF1
SAIF2
AHB Slave
APBX MASTER
AHB
AHB-to-APBX Bridge
AHB-to-APBX DMA
AUART0 RX
AUART0 TX
AUART1 RX
AUART2 RX
AUART1 TX
AUART2 TX
AHB Master
I2C0
I2C1
Freescale Semiconductor, Inc.

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