MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1083

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.5.4 Understanding Port Bandwidth
Each port has an associated bandwidth limit that sets the maximum percentage of the core
logic bandwidth that the port is allowed to use. Once this level is reached, the Arbiter will
no longer accept requests from this port until the bandwidth usage drops below the threshold.
This scheme allows for the bandwidth to be shared between the ports. If required, an overflow
option allows the port to continue to receive requests after the bandwidth limit has been
reached. See section
option.
The bandwidth limits are stored in the programmable parameters axiY_bdw for each port
Y at EMI initialization. The axiY_current_bdw parameters are used to track the actual
bandwidth utilized as computed by the bandwidth calculation module inside the Arbiter.
Port bandwidth is computed by counting the number of cycles that the core logic is busy
actively processing that port’s request in each 100 cycle period, referred to as the statistics
window.
In the EMI, 10 counters are used for this computation. The counters track the number of
active cycles in each statistics window, generating a moving average bandwidth value for
each port. This is the actual bandwidth utilized value saved in the current bandwidth
parameters (axiY_current_bdw). The values in the current bandwidth parameters are updated
every 10 cycles with the actual bandwidth used in the last 100 cycles.
The core logic is defined as actively processing for a port if any of the following situations
occur:
If all ports are assigned 100% bandwidth, then bandwidth usage will not factor and arbitration
will be purely based on priority.
The following figure shows bandwidth usage for a 4-port system with a 100-cycle calculation
window and 10 counters.
Freescale Semiconductor, Inc.
• The core logic is ready to transfer write data from the port to memory, but the data has
• The core logic is holding the port’s command and is ready to transfer to memory, but
• The core logic is actively transferring data from the port to memory.
• The core logic is ready to transfer read data from memory to the port but the port is
not arrived from the port.
is waiting to open a bank, precharge a bank, or some other memory-related action.
busy and unable to accept the data.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Understanding Port Bandwidth Hold-Off
Chapter 14 External Memory Interface (EMI)
for more information on this
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